INTEL

Company unveils new processing technology

As part of the Intel Architecture Day 2020 event, Intel unveiled a new version of 10 nm process technology called SuperFin. As the developers promise, this process technology allows the company to qualitatively improve the parameters of 10 nm semiconductor devices. SuperFin is considered Intel's most successful process optimization experience in Intel's history, and the effect of this can be compared to a real transition to "more refined" standards.
Of course, behind these claims of bravery is a certain amount of self-promotion, designed to hide Intel's inability to switch to real 7 nm process technology in the near future, which has been delayed until 2022 or even 2023. However , the new 10nm SuperFin process technology improves the performance of the transistor by 15-20% over the basic 10nm process used to make Ice Lake processors. And this progress is comparable to the effect achieved by a four-fold improvement in 14 nm process technology from the first Broadwell processors made with this technology to the most modern Cooper Lake.
The 10nm SuperFin technology will be used for the first time in Tiger Lake's next generation mobile processors, which are already in mass production and will begin shipping to customers before the Christmas holiday.



In the case of Tiger Lake, the new manufacturing technology allows for higher clock speeds with lower supply voltages and better energy efficiency, resulting in a wider clock frequency and voltage range. Peak frequencies for Tiger Lake are expected to be in the 5.0 GHz region, while current 10 nm Ice Lake processors are reaching just 4.1 GHz.
The 10 nm SuperFin technology incorporates improvements in the design of classic FinFET transistors, along with changes in metal interconnections. At the transistor level, these improvements include several things. First, an increase in tension in the crystalline structure of the epitaxial film at the source and in the drain, which results in a decrease in resistance and an increase in current through the channel. Second, the improvement of the door structure, which makes it possible to accelerate the movement of charge carriers through the transistor channel. And third, the ability to increase the gate pitch for better frequency scalability with increasing voltages.



As for metal joints, it is envisaged to use new variants of barrier dielectrics, which have a smaller thickness and allow to reduce the resistance of the interim joints by up to 30%. In addition, at the same time, a five-fold increase in capacitive resistance between the metal layers has been achieved, which results in a decrease in voltage drop with an increase in current vdroop and, consequently, in an overall improvement in stability semiconductor device. The new dielectric has a multilayer thin film structure and is composed of several materials with high dielectric constant in the medium, where each layer has a thickness of several angstroms. It should be noted that Intel introduced this dielectric for the first time in the industry and, in that regard, 10 nm SuperFin technology outperforms all technical processes available from other manufacturers.
In the future, Intel plans to carry out another optimization of 10 nm process technology: the subsequent process technology will be called Advanced 10 nm SuperFin. Additional steps will be needed to improve the performance of the transistor and make some new improvements to the interconnection. However, unlike the 10 nm SuperFin process, the next version of this technology is being designed with a focus on the data center processors known today as Sapphire Rapids.

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